System-Level Modelling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures
Title
System-Level Modelling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures
Price
€ 32,95
ISBN
9789056294557
Format
Paperback
Number of pages
154
Language
English
Publication date
Dimensions
15.6 x 32.4 cm
Table of Contents
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Table of Contents - 8 Acknowledgments - 6 1 Introduction 1.1 Related work in system-level design 1.2 Organization and contributions of this thesis 2 The Sesame environment 2.1 Trace-driven co-simulation 2.2 Application layer 2.3 Architecture layer 2.4 Mapping layer 2.5 Implementation aspects 2.5.1 Application simulator 2.5.2 Architecture simulator 2.6 Mapping decision support 2.7 Obtaining numbers for system-level simulation 2.8 Summary 3 Multiobjective application mapping 3.1 Related work on pruning and exploration 3.2 Problem and model definition 3.2.1 Application modeling 3.2.2 Architecture modeling 3.2.3 The mapping problem 3.2.4 Constraint linearizations 3.3 Multiobjective optimization 3.3.1 Preliminaries 3.3.2 Lexicographic weighted Tchebycheff method 3.3.3 Multiobjective evolutionary algorithms (MOEAs) 3.3.4 Metrics for comparing nondominated sets 3.4 Experiments 3.4.1 MOEA performance comparisons 3.4.2 Effect of crossover and mutation 3.4.3 Simulation results 3.5 Conclusion 4 Dataflow-based trace transformations 4.1 Traces and trace transformations 4.2 The new mapping strategy 4.3 Dataflow actors in Sesame 4.3.1 Firing rules for dataflow actors 4.3.2 SDF actors for architecture events 4.3.3 Token exchange mechanism in Sesame 4.3.4 IDF actors for conditional code and loops 4.4 Dataflow actors for event refinement 4.5 Trace refinement experiment 4.6 Conclusion 5 Motion-JPEG encoder case studies 5.1 Sesame: Pruning, exploration, and refinement 5.2 Artemis: Calibration and validation 5.3 Conclusion 6 Real-time issues 6.1 Problem definition 6.2 Recurring real-time task model 6.2.1 Demand bound and request bound functions 6.2.2 Computing request bound function 6.3 Schedulability under static priority scheduling 6.4 Dynamic priority scheduling 6.5 Simulated annealing framework 6.6 Experimental results 6.7 Conclusion 7 Conclusion A Performance metrics B Task systems References Nederlandse samenvatting Scientific output Biography

Cagkan Erbas

System-Level Modelling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures

Modern embedded systems come with contradictory design constraints. On one hand, these systems often target mass production and battery-based devices, and therefore should be cheap and power efficient. On the other hand, they still need to show high (sometimes real-time) performance, and often support multiple applications and standards which requires high programmability. This wide spectrum of design requirements leads to complex heterogeneous System-on-Chip (SoC) architectures -- consisting of several types of processors from fully programmable microprocessors to configurable processing cores and customized hardware components, integrated on a single chip. This study targets such multiprocessor embedded systems and strives to develop algorithms, methods, and tools to deal with a number of fundamental problems which are encountered by the system designers during the early design stages.
Author

Cagkan Erbas

Cagkan Erbas received his BSc degree in electrical engineering from the Middle East Technical University, Ankara and his MSc degree in computer engineering from the Ege University, Izmir. He completed his PhD thesis in 2006 at the University of Amsterdam, where he is currently a postdoc researcher working on multiprocessor embedded systems.